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? semiconductor components industries, llc, 2015 september, 2015 ? rev. 4 1 publication order number: NCV97310/d NCV97310 automotive battery- connected low-iq multi- output power management unit with 3 buck regulators description the NCV97310 is a 3?output regulator consisting of a low?iq battery?connected 3 a, 2 mhz non?synchronous switcher and two low?voltage 1.5 a, 2 mhz synchronous switchers; all using integrated power transistors. the high?voltage switcher is capable of converting a 4.1 v to 18 v battery input to a 5 v or 3.3 v output at a constant 2 mhz switching frequency, delivering up to 3 a. in overvoltage conditions up to 36 v, the switching frequency folds back to 1 mhz; in load dump conditions up to 45 v the regulator shuts down. the output of the battery?connected buck regulator serves as the low voltage input for the 2 downstream synchronous switchers. each downstream output is adjustable from 1.2 v to 3.3 v, with a 1.5 a average current limit and a constant 2 mhz switching frequency. each switcher has an independent enable and reset pin, giving extra power management flexibility. for low?iq operating mode, the low?voltage switchers are disabled and the standby rail is supplied by a low?iq ldo (up to 150 ma) with a typical iq of 30 a. the ldo regulator is in parallel to the high?voltage switcher, and is activated when the switcher is forced in standby mode. all 3 smps outputs use peak current mode control with internal slope compensation, internally?set soft?start, battery undervoltage lockout, battery overvoltage protection, cycle?by?cycle current limiting, hiccup mode short?circuit protection and thermal shutdown. an error flag is available for diagnostics. features ? 5.0 v and 3.3 v versions available ? low quiescent current in standby mode ? programmable spread spectrum for emi reduction ? 2 microcontroller enabled low voltage synchronous buck converters ? large conversion ratio of 18 v to 3.3 v battery connected switcher ? wide input of 4.1 to 45 v with undervoltage lockout (uvlo) ? fixed frequency operation adjustable from 2.0 to 2.6 mhz ? internal 1.5 ms soft?starts ? cycle?by?cycle current limit protections ? hiccup overcurrent protections (ocp) ? individual reset pins with adjustable delays ? qfn package with wettable flanks (pin edge plating) ? ncv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable ? these devices are pb?free, halogen free/bfr free and are rohs compliant typical applications ? infotainment, body electronics, telematics, ecu www. onsemi.com marking diagram qfn32 mw suffix case 488am 32 1 NCV97310 xx awlyyww 1 xx = 33 or 50 a = assembly location wl = wafer lot yy = year ww = work week = pb?free package see detailed ordering, marking and shipping information on page 24 of this data sheet. ordering information (note: microdot may be in either location)
NCV97310 www. onsemi.com 2 figure 1. NCV97310 block diagram ? 5.0 v version linear regulator err osc regulator 1 5.0 v step down regulator 2 1.2 v ??> 3.3 v step down regulator 3 1.2 ??> 3.3 v step down vinl vout vbat sw1 en stbyb vin2 sw2 sw3h fb2 fb3 en2 en3 vdrv1 bst1 rosc ot warning vin_uvlo errb gnd2 rstb1 rstb2 temp vin_ov rstb1 rstb2 rstb3 gnd1 bst2 bst3 rmin rstb3 vdd vdrv vdrv2 sw3l gnd3 master enable rstb rstb rstb comp1 vdrv vin3 rmod rdepth logic exposed pad
NCV97310 www. onsemi.com 3 linear regulator err osc regulator 1 3.3 v step down regulator 2 1.2 v ??> 3.3 v step down regulator 3 1.2 v ??> 3.3 v step down vinl vout vbat sw1 en stbyb vin2 sw2 sw3h fb2 fb3 en2 en3 vdrv1 bst1 rosc ot warning vin_uvlo errb gnd2 rstb1 rstb2 temp vin_ov rstb1 rstb2 rstb3 gnd1 bst2 bst3 nc rstb3 vdd vdrv vdrv2 sw3l gnd3 master enable rstb rstb rstb comp1 vdrv vin3 rmod rdepth figure 2. NCV97310 block diagram ? 3.3 v version exposed pad
NCV97310 www. onsemi.com 4 typical application figure 3. typical application ? 5.0 v version 32 25 9 16 24 17 1 8 vbat en stbyb rstb1 comp1 rosc errb en2 rstb2 gnd1 rstb3 fb3 en3 bst3 gnd3 sw3l sw3h vdrv2 gnd2 sw2 vin2 rmin sw1 vdrv1 bst1 vinl vout fb2 bst2 vin3 rdepth rmod v bat d 1 l 1 c bst1 c drv1 c in1 r depth r mod r osc r comp1 c comp1 c bst2 r fb2d c out1 v out1 v out2 l 2 c out2 r fb2u c drv2 c in2 l 3 v out3 c out3 c bst3 r fb3u r min exposed pad
NCV97310 www. onsemi.com 5 figure 4. typical application ? 3.3 v version 32 25 9 16 24 17 1 8 vbat en stbyb rstb1 comp1 rosc errb en2 rstb2 gnd1 rstb3 fb3 en3 bst3 gnd3 sw3l sw3h vdrv2 gnd2 sw2 vin2 nc sw1 vdrv1 bst1 vinl vout fb2 bst2 l 1 c bst1 c drv1 d 1 c drv2 c bst2 r fb2d r fb2u c out2 l 2 r fb3u c bst3 r osc r comp1 c comp1 v out2 v out3 c out3 l 3 v out1 c out1 v bat c in2 c in1 vin3 r mod r depth rdepth rmod exposed pad
NCV97310 www. onsemi.com 6 table 1. maximum ratings rating symbol value unit min/max voltage vbat, vinl ?0.3 to 45 v max voltage vbat to sw1 45 v min/max voltage sw1 ?0.7 to 40 v min voltage sw1, sw2, sw3 ? 20 ns ?3.0 v min/max voltage bst1, stbyb, en ?0.3 to 40 v min/max voltage vin2, vin3, bst2, bst3, sw2, sw3h, sw3l, vout, rmin ?0.3 to 12 v min/max voltage on rstb2, rstb3, en2, en3, fb2, fb3 ?0.3 to 6 v min/max voltage on rstb1, errb (3.3 v version) ?0.3 to 3.6 v min/max voltage on rstb1, errb (5.0 v version) ?0.3 to 6 v max voltage bst1 to sw1, bst2 to sw2, bst3 to sw3x 3.6 v min/max voltage vdrv1, vdrv2, comp1, rosc, rmod, rdepth ?0.3 to 3.6 v thermal resistance, 5 x 5 qfn junction ? to ? ambient (note 1) r ja 25 c/w storage temperature range ?55 to +150 c operating junction temperature range t j ?40 to +150 c esd withstand voltage human body model machine model v esd 2.0* 200 kv v moisture sensitivity msl level 1 peak reflow soldering temperature 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. mounted on 1 sq. in. of a 4?layer pcb with 1 oz. copper thickness. *bst2, bst3 hbm 1.5 kv table 2. recommended operating conditions rating value vin range 4.5 v to 36 v ambient temperature range ?40 c to 125 c functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability.
NCV97310 www. onsemi.com 7 table 3. pin function descriptions pin no. symbol description 1 vbat input voltage from battery. place an input filter capacitor in close proximity to this pin. must be tied to pin 29 ? vinl. 2 en high?voltage (battery), ttl?compatible, master enable signal. grounding this input stops all outputs and reduces iq to a minimum (shutdown mode). 3 stbyb high?voltage (battery), ttl?compatible, mode selection signal. grounding this input activates the low?iq mode of operation for switcher 1 (standby mode). 4 rdepth modulation depth adjustment (% of fsw) for spread spectrum. set with a resistor to gnd. 5 rmod modulation frequency adjustment for spread spectrum. set with a resistor to gnd. 6 rstb1 reset with adjustable delay. goes low when the output is out of regulation. 7 comp1 output of the error amplifier for switcher 1 8 rosc provides frequency adjustment 9 errb error flag combining temperature and input and output voltage sensing 10 en2 ttl compatible low voltage input. grounding this input stops switcher 2. 11 rstb2 reset with adjustable delay. goes low when the output is out of regulation. 12 gnd1 ground reference for the ic. 13 rstb3 reset with adjustable delay. goes low when the output is out of regulation. 14 fb3 output voltage sensing, provides adjustability. 15 en3 ttl compatible low voltage input. grounding this input stops switcher 3. 16 bst3 bootstrap input provides drive voltage higher than vin3 to the high?side n?channel switch for optimum switch r ds(on) and highest efficiency. 17 gnd3 ground connection for the source of the low?side switch of switcher 3. 18 sw3l drain of the low?side switch. connect the output inductor to this pin. must be tied to sw3h. 19 sw3h source of the high?side switch. connect the output inductor to this pin. must be tied to sw3l. 20 vdrv2 internal supply voltage for driving the low?voltage internal switches. connect a capacitor for noise filtering purposes. 21 vin3 low input voltage for switcher 3. place an input filter capacitor in close proximity to this pin. must be connected to pin 22 ? vin2 and pin 28 ? vout. 22 vin2 low input voltage for switcher 2. place an input filter capacitor in close proximity to this pin. must be connected to pin 21 ? vin3 and pin 28 ? vout. 23 sw2 switching node of the switcher 2 regulator. connect the output inductor to this pin. 24 gnd2 ground connection for the source of the low?side switch of switcher 2. 25 bst2 bootstrap input provides drive voltage higher than vin2 to the high?side n?channel switch for optimum switch r ds(on) and highest efficiency. 26 rmin 5.0 v version: minimum load pull?down for switcher mode. connect a resistor to vout1, if needed (see applications section for details). nc 3.3 v version: this pin is a no?connect. leave the pin floating. 27 fb2 output voltage sensing, provides adjustability. 28 vout output voltage sensing. delivers the output current in low?iq mode 29 vinl input voltage from battery. place an input filter capacitor in close proximity to this pin. must be tied to pin1 ? vbat. 30 bst1 bootstrap input provides drive voltage higher than vbat to the n?channel power switch for optimum switch rdson and highest efficiency. 31 vdrv1 internal supply voltage for driving the low?voltage internal switch. connect a capacitor for noise filtering purposes. 32 sw1 switching node of the regulator. connect the output inductor and cathode of the freewheeling diode to this pin. exposed pad must be connected to gnd1 (electrical ground) and to a low thermal resistance path to the ambient temperature environment.
NCV97310 www. onsemi.com 8 table 4. electrical characteristics (v bat = v inl = 4.5 v to 28 v, v en = v stbyb = v en2 = v en3 = 5 v, v bstx = v swx + 3.0 v, c drv1 = 0.1 f, c drv2 = 0.47 f. min/max values are valid for the temperature range ?40 c t j 150 c unless noted otherwise, and are guaranteed by test, design or statistical correlation.) parameter symbol conditions min typ max unit quiescent current quiescent current, shutdown i qsd v bat = v inl = 13.2 v, t j = 25 c, v en = 0 v 8 12 a quiescent current, standby i qen v bat = v inl = 13.2 v, t j = 25 c v en = 3 v, v stbyb = v en2 = v en3 = 0 v 25 35 a undervoltage lockout ? vbat (uvlo) vbat uvlo start threshold v uv1st v bat rising 4.45 4.85 v vbat uvlo stop threshold v uv1sp v bat falling 3.7 4.1 v vbat uvlo hysteresis v uv1hy 0.75 v enable logic low (voltage input needed to guarantee logic low) v enlo , v en2lo , v en3lo , v stbyblo 0.8 v logic high (voltage input needed to guarantee logic high) v enhi , v en2hi , v en3hi , v stbybhi 2 v enable pin input current i en v en = 5 v 0.125 1.0 a i stbyb v stbyb = 5 v 0.5 2.0 i en2 , i en3 v en2 = v en3 = 5 v 30 50 70 switcher 1 start?up time t stbyb stbyb ?high? to switcher 1 ready 60 200 s output voltage switcher 1 output v out 5.0 v version 3.3 v version 4.9 3.23 5.0 3.3 5.1 3.37 v v out line regulation in low?iq mode v line1 i out = 50 ma, v stbyb = 0 v, 6 v < v inl = v bat < 28 v 5 25 mv v out load regulation in low?iq mode v load1 v inl = v bat = 13.2 v, v stbyb = 0 v, 1 ma < i out < 150 ma 10 35 mv voltage drop?out in low?iq mode v drop1 i out = 150 ma, v stbyb = 0 v 500 mv switchers 2 and 3 fb pin voltage during regulation v fb2r , v fb3r outx connected to fbx through a 10 k resistor 1.179 1.200 1.221 v error amplifier ? switcher 1 transconductance (note 2) g m g m(hv) v comp = 1.1 v 4.5 v < v bat < 18 v 20 v < v bat < 28 v 0.6 0.35 1.0 0.55 1.4 0.75 mmho output resistance r out 1.4 m comp source current limit i source v out = 4.0 v, v comp = 1.1 v 4.5 v < v bat < 18 v 20 v < v bat < 28 v 50 25 75 40 100 55 a comp sink current limit i sink v out = 6.0 v, v comp = 1.1 v 4.5 v < v bat < 18 v 20 v < v bat < 28 v 50 25 75 40 100 55 a minimum comp voltage v cmpmin v out = 6.0 v 0.15 0.3 v maximum comp voltage v cmpmax v out = 4.0 v 1.3 1.6 v product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 2. not tested in production. limits are guaranteed by design. 3. minimum load parameters are only valid for the 5.0 v version, opn: NCV97310mw50r2g
NCV97310 www. onsemi.com 9 table 4. electrical characteristics (v bat = v inl = 4.5 v to 28 v, v en = v stbyb = v en2 = v en3 = 5 v, v bstx = v swx + 3.0 v, c drv1 = 0.1 f, c drv2 = 0.47 f. min/max values are valid for the temperature range ?40 c t j 150 c unless noted otherwise, and are guaranteed by test, design or statistical correlation.) parameter unit max typ min conditions symbol oscillator switching frequency ? switcher 1 f sw1 f sw1(hv) 4.5 < v bat < 18 v, r osc = open 20 v < v bat < 28 v, r osc = open 1.8 0.9 2.0 1.0 2.2 1.1 mhz switching frequency ? switchers 2 & 3 f sw2 , f sw3 r osc = open 1.8 2.0 2.2 mhz switching frequency ? r osc f rosc r osc = 12.5 k 2.3 2.5 2.8 mhz r osc reference voltage v rosc r osc = 25 k 0.9 1.0 1.1 v vbat overvoltage shutdown monitor overvoltage stop threshold v ov1sp 36 v overvoltage start threshold v ov1st 30 v overvoltage hysteresis v ov1hy 0.6 1.4 2.4 v vbat frequency foldback monitor frequency foldback threshold v fl1u v fl1d v bat rising v bat falling 18.4 18 20 19.8 v frequency foldback hysteresis v fl1hy 0.2 0.3 0.4 v soft?start soft?start completion time t ss1 , t ss2 , t ss3 0.8 1.4 2.0 ms slope compensation ramp slope (note 2) ? switcher 1 (with respect to switch current) s ramp1 s ramp1(hv) 4.5 < v bat < 18 v 20 v < v bat < 28 v 1.8 0.8 3.4 1.6 a/ s ramp slope (note 2) ? switchers 2 & 3 s ramp2 1.9 3.7 a/ s power switch ? switcher 1 on resistance r ds1on v bst1 = v sw1 + 3.0 v, i sw1 = 500 ma 185 360 m leakage current vbat to sw1 i lksw1 v en = 0 v, v sw1 = 0, v bat = 18 v 10 a minimum on time t on1min measured at sw1 pin 45 70 ns minimum off time t off1min measured at sw1 pin 30 50 70 ns power switches ? switcher 2 high?side on resistance r hs2on v bst2 = v sw2 + 3.0 v, i sw2 = 500 ma 165 300 m low?side on resistance r ls2on i sw2 = 500 ma 130 230 m leakage current high?side switch i lksw2 v en2 = 0 v, v sw2 = 0, v in2 = 5.5 v 5 a minimum on time t on2min measured at sw2 pin 60 80 95 ns minimum off time t off2min measured at sw2 pin 35 55 75 ns non?overlap time t novlp 10 ns power switches ? switcher 3 high?side on resistance r hs3on v bst3 = v sw3h + 3.0 v, i sw3h = 500 ma 140 250 m low?side on resistance r ls3on i sw3l = 500 ma 130 230 m leakage current high?side switch i lksw3 v en3 = 0 v, v sw3h = 0, v in3 = 5.5 v 5 a minimum on time t on3min measured at sw3x pin 60 80 95 ns minimum off time t off3min measured at sw3x pin 35 55 75 ns product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 2. not tested in production. limits are guaranteed by design. 3. minimum load parameters are only valid for the 5.0 v version, opn: NCV97310mw50r2g
NCV97310 www. onsemi.com 10 table 4. electrical characteristics (v bat = v inl = 4.5 v to 28 v, v en = v stbyb = v en2 = v en3 = 5 v, v bstx = v swx + 3.0 v, c drv1 = 0.1 f, c drv2 = 0.47 f. min/max values are valid for the temperature range ?40 c t j 150 c unless noted otherwise, and are guaranteed by test, design or statistical correlation.) parameter unit max typ min conditions symbol power switches ? switcher 3 non?overlap time t novlp 10 ns peak current limits current limit threshold ? switcher 1 normal mode low?iq mode i lim1 i lim1,stby v stbyb = 5 v v stbyb = 0 v 3.9 0.15 4.4 0.2 4.9 0.25 a current limit threshold ? switcher 2 i lim2 2.6 2.9 3.2 a current limit threshold ? switcher 3 i lim3 2.6 2.9 3.2 a short circuit frequency foldback ? switcher1 lowest foldback frequency lowest foldback frequency ? high v in f sw1af f sw1afhv v out = 0 v, 4.5 v < v bat < 18 v v out = 0 v, 20 v < v bat < 28 v 450 225 550 275 650 325 khz hiccup mode hiccup mode f sw1hic , f sw2hic , f sw3hic v swx = 0 v 24 32 40 khz reset reset threshold ? switcher 1 (as a ratio of v out1 ) k res_lo1 k res_hi1 v out1 decreasing v out1 increasing 90 90.5 92.5 95 97 % reset threshold ? switchers 2 & 3 (at fbx) k res_lo2 k res_hi2 fbx decreasing fbx increasing 1.1 1.164 v reset hysteresis (ratio of voutx) k res_hys 0.5 % noise?filtering delay t res_filt 5 25 s reset delay time t reset i rstbx = 2 ma i rstbx = 1 ma i rstbx = 100 a 3.5 15 1.0 4.5 30 5.5 50 s ms ms reset output low level v resl i rstbx = 2 ma 0.4 v bootstrap voltage supply output voltage v drv1 , v drv2 3.1 3.3 3.5 v v drvx por start threshold v drv1st v drv2st 2.7 2.35 2.85 2.5 3.05 2.65 v v drvx por stop threshold v drv1sp v drv2sp 2.55 2.2 2.75 2.35 2.95 2.5 v minimum load ? 5.0 v version (note 3) rmin saturation voltage v rmin i rmin = 100 ma into the pin 0.9 2.9 v vbat threshold to activate rmin v rmin_th 7.2 7.5 7.9 v spread spectrum rmod pin voltage v rmod r mod = 10 k 0.54 0.60 0.66 v rdepth pin voltage v rdepth r depth = 10 k 0.54 0.60 0.66 v modulation frequency f mod rmod = rdepth = 10 k 22 25 28 khz modulation depth (top frequency) f depth,max rmod = rdepth = 10 k 2.05 2.3 2.55 mhz spread spectrum disable r ssdis rmod or rdepth 1.7 150 k product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 2. not tested in production. limits are guaranteed by design. 3. minimum load parameters are only valid for the 5.0 v version, opn: NCV97310mw50r2g
NCV97310 www. onsemi.com 11 table 4. electrical characteristics (v bat = v inl = 4.5 v to 28 v, v en = v stbyb = v en2 = v en3 = 5 v, v bstx = v swx + 3.0 v, c drv1 = 0.1 f, c drv2 = 0.47 f. min/max values are valid for the temperature range ?40 c t j 150 c unless noted otherwise, and are guaranteed by test, design or statistical correlation.) parameter unit max typ min conditions symbol error flag errb output low level v errbl i errb = 1 ma 0.4 v thermal shutdown thermal warning activation temperature (note 2) t warn 150 c thermal shutdown activation temperature (note 2) t sd 150 190 c hysteresis (note 2) t hys 5 20 c product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 2. not tested in production. limits are guaranteed by design. 3. minimum load parameters are only valid for the 5.0 v version, opn: NCV97310mw50r2g
NCV97310 www. onsemi.com 12 typical characteristics figure 5. quiescent current (shutdown) vs. junction temperature figure 6. quiescent current (standby) vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 15 figure 7. uvlo vs. junction temperature figure 8. vout vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) figure 9. sw2 vref vs. junction temperature figure 10. sw3 vref vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) i qsd , quiescent current, shutdown ( a) i qen , quiescent current, standby ( a) uvlo (v) vout, ldo (v) vref, sw2 (v) vref, sw3 (v) 150 125 100 75 50 25 0 ?25 ?50 25 150 125 100 75 50 25 0 ?25 ?50 3.0 3.5 4.0 5.0 5.5 150 4.5 125 100 75 50 25 0 ?25 ?50 4.970 4.980 4.990 5.000 5.010 150 4.975 4.985 4.995 5.005 125 100 75 50 25 0 ?25 ?50 1.2014 150 125 100 75 50 25 0 ?25 ?50 1.2011 150 rising falling 1 ma 150 ma 14 13 12 11 10 9 8 7 6 5 24 23 22 21 20 19 18 17 16 15 1.2012 1.2010 1.2008 1.2006 1.2004 1.2002 1.2010 1.2009 1.2008 1.2007 1.2006 1.2005 1.2004 1.2003
NCV97310 www. onsemi.com 13 typical characteristics figure 11. f sw vs. junction temperature t j , junction temperature ( c) f sw (mhz) 125 100 75 50 25 0 ?25 ?50 150 2.016 2.014 2.012 2.010 2.008 2.006 2.004 2.002 2.000 figure 12. soft start time vs. junction temperature t j , junction temperature ( c) soft start time (ms) 125 100 75 50 25 0 ?25 ?50 150 1.7 sw1 sw3 sw2 1.65 1.6 1.55 1.5 1.45 1.4 figure 13. sw1 r ds(on) vs. junction temperature figure 14. sw2 high side r ds(on) vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) r ds(on) , sw1 (m ) r hs2(on) , sw2 (m ) 125 100 75 50 25 0 ?25 ?50 0 100 150 250 150 50 200 300 125 100 75 50 25 0 ?25 ?50 0 100 150 250 150 50 200 300 figure 15. sw2 low side r ds(on) vs. junction temperature figure 16. sw3 high side r ds(on) vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) r ls2(on) , sw2 (m ) r hs3(on) , sw3 (m ) 125 100 75 50 25 0 ?25 ?50 0 100 150 250 150 50 200 125 100 75 50 25 0 ?25 ?50 0 100 150 250 150 50 200
NCV97310 www. onsemi.com 14 typical characteristics figure 17. sw3 low side r ds(on) vs. junction temperature figure 18. ldo current limit vs. junction temperature t j , junction temperature ( c) t j , junction temperature ( c) r ls3(0n) , sw3 (m ) current limit, ldo (ma) 125 100 75 50 25 0 ?25 ?50 0 150 50 100 150 200 250 125 100 75 50 25 0 ?25 ?50 150 202 201 200 199 198 197 196 195 figure 19. sw1 peak current limit vs. junction temperature t j , junction temperature ( c) peak current limit, sw1 (ma) 125 100 75 50 25 0 ?25 ?50 4560 150 4540 4520 4500 4480 4460 4440 4420 4400 4380 figure 20. sw2 peak current limit vs. junction temperature t j , junction temperature ( c) peak current limit, sw2 (ma) 125 100 75 50 25 0 ?25 ?50 2860 15 0 2850 2840 2830 2820 2810 2800 2790 figure 21. sw3 peak current limit vs. junction temperature t j , junction temperature ( c) peak current limit, sw3 (ma) 125 100 75 50 25 0 ?25 ?50 2930 150 2920 2910 2900 2890 2880 2870 2860 2850 figure 22. vdrv1 voltage vs. junction temperature t j , junction temperature ( c) vdrv1 (v) 125 100 75 50 25 0 ?25 ?50 150 3.3325 3.332 3.3315 3.331 3.3305 3.33
NCV97310 www. onsemi.com 15 typical characteristics figure 23. vdrv2 voltage vs. junction temperature t j , junction temperature ( c) 125 100 75 50 25 0 ?25 ?50 vdrv2 (v) 150 3.2985 3.298 3.2975 3.297 3.2965 3.296 3.2955 3.295
NCV97310 www. onsemi.com 16 application information general description the NCV97310 consists of one 2 mhz battery?connected 2.5 a switcher (switcher 1) with a parallel low?iq 150 ma ldo, and two low?voltage 2 mhz 1.5 a switchers (switchers 2 and 3). linear regulator err osc regulator 1 5v or 3v3 step down regulator 2 1v2 ... 3v3 step down regulator 3 1v2...3v3 step down vinl vout vbat sw1 en stbyb vin2 sw2 sw3h fb2 fb3 en2 en3 vdrv1 bst1 rosc ot warning vin_uvlo errb gnd2 rstb1 rstb2 temp vin_ov rstb1 rstb2 rstb3 gnd1 bst2 bst3 rmin rstb3 vdd vdrv vdrv2 sw3l gnd3 master enable rstb rstb rstb comp1 vdrv vin3 rmod rdepth logic figure 24. NCV97310 block schematic switcher 2 switcher 3 switcher 1 and low?iq ldo exposed pad
NCV97310 www. onsemi.com 17 common blocks input voltage the main supply for the part is taken from the vbat pin, which much always be tied to a voltage source between 4.1 v and 36 v. ? below 4.1 v an undervoltage lockout (uvlo) circuit inhibits all switching, resets the soft?start circuits, and turns off the ldo. ? above 36 v, an overvoltage shutdown circuit inhibits all switching and allows the NCV97310 to survive a 45 v load dump. normal operation resumes when vbat goes back down below 30 v. although the ldo has its own input pin vinl (that can also survive a 45 v load dump), it must always be connected to vbat for proper operation. s witcher 2 and switcher 3 each have a dedicated input pin, vin2 and vin3. vin2 and vin3 should be shorted together right at the pin because they share a common drive pin, vdrv2. please note that vin2 and vin3 are strictly low voltage (up to 12 v when disabled and 9.5 v when switching) and there is no voltage sensing present. it is recommended to connect vin2 (and vin3) to vout1, although a different rail could be used to supply switchers 2 and 3, as long as vba t is powered and switcher 1 enabled (see oscillator section for details). oscillator all three switchers share the same oscillator, which defaults to 2.0 mhz and can be adjusted from 2.0 to 2.6 mhz using an external resistor (r osc ) to ground. the range of rosc value for this range of frequency adjustment is between 12.5 k and 50 k (see figure 25). for resistor values below 10 k , the frequency is safely clamped to 2.8 mhz. instead of a resistor, one can force a current out of the rosc pin, between 20 a (corresponding to 2 mhz) and 80 a (corresponding to 2.5 mhz), typical. figure 25. oscillator frequency vs. rosc value 0 10 2030405060 r osc , (k ) oscillator frequency (mhz) 3.0 2.8 2.6 2.4 2.2 2.0 1.8 manually adjusting the oscillator frequency using the rosc pin changes the switching frequency of all 3 switchers, since they share a common oscillator. when switcher 1 enters maximum duty cycle frequency foldback, though, switchers 2 and 3 remain at their nominal switching frequency. the foldback for switcher 1 takes place in logic outside of the oscillator. the same applies for both switcher 2 and switcher 3. when switcher 2, for example, enters maximum duty cycle frequency foldback, the other two switchers remain at their nominal switching frequency. spread spectrum in smps devices, switching translates to higher efficiency. unfortunately, the switching leads to a much noisier emi profile. we can greatly decrease some of the radiated emissions with some spread spectrum techniques. spread spectrum is used to reduce the peak electromagnetic emissions of a switching regulator. f c 9f c 7f c 5f c 3f c f c 9f c 7f c 5f c 3f c t t v v time domain frequency domain unmodulated modulated figure 26. the spread spectrum used in the NCV97310 is an ?up?spread? technique, meaning the switching frequency is spread upward from the 2.0 mhz base frequency. for example, a 5% spread means that the switching frequency is swept (spread) from 2.0 mhz up to 2.1 mhz in a linear fashion ? this is called the modulation depth. the rate at which this spread takes place is called the modulation frequency. for example, a 10 khz modulation frequency means that the frequency is swept from 2.0 mhz to 2.1 mhz in 50 s and then back down from 2.1 mhz to 2.0 mhz in 50 s.
NCV97310 www. onsemi.com 18 figure 27. the modulation depth and modulation frequency are each set by an external resistor to gnd. the modulation frequency can be set from 5 khz up to 50 khz using a resistor from the rmod pin to gnd. the modulation depth can be set from 3% up to 30% of the nominal switching frequency using a resistor from the rdepth pin to gnd. please see the curves below for typical values: figure 28. modulation frequency vs. rmod value r mod , (k ) modulation frequency (khz) 52 47 42 37 32 27 22 17 12 7 2 0102030405060 figure 29. modulation depth vs. rdepth value r depth , (k ) modulation depth (%fsw) 35 010203040506 0 30 25 20 15 10 5 0 spread spectrum is automatically turned off when there is a short to gnd or an open circuit on either the rmod pin or the rdepth pin. please be sure that the rosc pin is an open circuit when using spread spectrum. spread spectrum is automatically turned off when there is a short to gnd or an open circuit on either the rmod pin or the rdepth pin. please be sure that the rosc pin is an open circuit when using spread spectrum. master enable the NCV97310 can be completely disabled (shutdown mode) by connecting the en pin to ground. as a result, all outputs are stopped and the internal current consumption drops below 10 a. the en pin is designed to accept either a logic level signal or the battery voltage. reset when the voltage on the outx pin drops below the reset threshold (92.5% typically for rstb1, 93.5% typically for rstb2 & rstb3), the open?drain output rstbx is pulled low. the rstb1 pin is fully operational in low?iq mode. the rstb2 & rstb3 pins are asserted (pulled low) when the associated switcher is disabled and when in low?iq mode (stbyb low). delay each of the rstb signals can either be used as a reset with delay or a power good (no delay). the delay is determined by the current into the rstbx pin, set by a resistor, shown in figure 30. r rstbx vout1 rstx rstbx figure 30. reset delay time use the following equation to determine the ideal reset delay time using currents less than 1 ma: t delay 3000 i rstbx 1.2 (eq. 1) where: t delay : ideal reset delay time [ms] i rstbx : current into the rstbx pin [ a] using i rstbx = 2 ma removes the delay and allows the reset to act as a ?power good? pin. the rstbx resistor is commonly tied to vout1. for the 5.0 v version, typical delay times can be achieved with the following resistor values:
NCV97310 www. onsemi.com 19 r rstbx (k ? ) t dly (ms) 5 4.4 10 7.3 20 13.0 30 18.8 50 31.5 for the 3.3 v version, typical delay times can be achieved with the following resistor values: r rstbx (k ? ) t dly (ms) 3.3 4.5 5 5.9 10 10.3 20 19.3 30 28.9 minimum dropout voltage when operating at low input voltages, two parameters play a major role in imposing a minimum voltage drop across the regulator: the minimum off time (that sets the maximum duty cycle) and the on?state resistance. when operating in continuous conduction mode (ccm), the output voltage is equal to the input voltage multiplied by the duty ratio. because each switcher needs a sufficient bootstrap voltage to operate, its duty cycle cannot be 100%: it needs a minimum off time (t off,min ) to periodically re?fuel the bootstrap capacitor, c bst . this imposes a maximum duty ratio d max = 1 ? t off,min ? f sw(min) with the switching frequency being folded back to f sw(min) = 500 khz to keep regulating at the lowest input voltage possible. the drop due to the on?state resistance is simply the voltage drop across the switch at the given output current: v sw,drop = i out ? r ds(on) . which leads to the maximum output voltage in low vin condition: v out = d max ? v in(min) ? v sw,drop error flag an open drain errb pin (active low) flags the status of several internal error detectors: vbat undervoltage, vbat overvoltage, thermal warning, switcher 1 reset, as well as the reset flags rstb2 and rstb3 if their respective switchers are enabled. note that overvoltage is not flagged in low?iq standby mode. when the master enable pin en is forced low, the error flag is not active anymore. thermal shutdown a thermal shutdown circuit inhibits switching, resets the soft?start circuits, and removes drvx voltages if the internal temperature exceeds a safe level. switching is automatically restored when the temperature returns to a safer level. inductor selection by default, a 4.7 h inductor is recommended for the primary switching output. if you?d like to choose a dif ferent value, please follow the equation, below. l v out 1 v out v in,max i r f sw i out where: v out : dc output voltage [v] v in,max : maximum dc input voltage [v] i r : inductor current ripple [%] f sw : switching frequency [hz] i out : dc output current [a] discontinuous mode in order to ensure continuous conduction mode, the ripple (half of the peak?to?peak ripple) needs to be less than the average current through the inductor. the limit can be found using the following equation for borderline conduction mode: i bcm 1 2 1 v out v in,max f sw v out l where: i bcm : borderline conduction mode output current [a] v out : dc output voltage [v] v in,max : maximum dc input voltage [v] f sw : switching frequency [hz] l: inductor value [h] average output currents above i bcm will operate in continuous mode while average output currents below i bcm will operate in discontinuous mode.
NCV97310 www. onsemi.com 20 switcher 1 output voltage the NCV97310 comes in a 5.0 v version and a 3.3 v version. the output of switcher 1, as well as the output of the low?iq ldo, are fixed at 5.0 v and 3.3 v, respectively. high voltage frequency foldback to limit the power lost in generating the drive voltage for the power switch, the switching frequency is reduced by a factor of 2 when the input voltage exceeds the v bat frequency foldback threshold v fl1u (see figure 31). frequency reduction is automatically terminated when the input voltage drops back below the v bat frequency foldback threshold v fl1d . 4 18 20 36 1 2 45 30 figure 31. switcher 1 switching frequency reduction at high input voltage f sw (mhz) v in (v) low?iq mode the NCV97310 can be put in a low?iq regulating mode by connecting the stbyb pin to ground. as a result, switcher 1 turns off and the low?iq ldo turns on, maintaining regulation on vout (up to 150 ma). in this mode the vout reset monitor is still active (rstb1 pin), as well as the under?voltage sensing on vbat and the thermal sensing, and they?re all flagged on the errb pin. switchers 2 and 3 are automatically disabled, with their respective reset pins pulled low. upon enabling, voltage is established at the drv1 pin, followed by a pre?charge of the bootstrap capacitor before switcher 1 starts switching. there is no soft?start unless vout is below the reset threshold it is recommended to wait at least 200 s after toggling stbyb before applying a load higher than 150 ma. the stbyb pin is designed to accept either a logic level signal or the battery voltage. soft?start upon being enabled or released from a fault condition, and after the drv1 voltage is established, a soft?start circuit ramps the switching regulator error amplifier reference voltage to the final value. during soft?start, the average switching frequency is lower than its normal mode value (typically 2 mhz) until the output voltage approaches regulation. there is no soft?start if the output is already above the reset threshold. error amplifier the error amplifier is a transconductance type amplifier. the output voltage of the error amplifier controls the peak inductor current at which the power switch shuts off. the current mode control method employed allows the use of a simple, type ii compensation to optimize the dynamic response according to system requirements. the compensation components must be connected between the output of the error amplifier and the electrical ground (between pins comp1 and gnd1). for most applications, the following compensation circuitry is recommended: 330 pf 12.4k 22 pf comp figure 32. recommended compensation for primary switcher slope compensation a fixed slope compensation signal is generated internally and added to the sensed current to avoid increased output voltage ripple due to bifurcation of inductor ripple current at duty cycles ab ove 50% (sub?harmonics oscillations). the fixed amplitude of the slope compensation signal requires the inductor to be greater than a minimum value, depending on output voltage, in order to avoid sub?harmonic oscillations. for both 3.3 v and 5.0 v versions, the recommended inductor value is either 2.2 h or 4.7 h. to determine the minimum inductor required to avoid sub?harmonic oscillations, please refer to the following equation: l min v out 2*s ramp where: l min : minimum inductor required to avoid sub-harmonic oscillations [ h]
NCV97310 www. onsemi.com 21 v out : output voltage [v] s ramp : internal slope compensation [a/ s] short circuit frequency foldback during severe output overloads or short circuits, switcher 1 automatically reduces its switching frequency. this creates duty cycles small enough to limit the peak current in the power components, while maintaining the ability to automatically reestablish the output voltage if the overload is removed. if the current is still too high after the switching frequency folds back to 500 khz (250 khz for v in > 20 v), the regulator enters hiccup mode (32 khz) that further reduces the dissipated power. bootstrap at the drv1 pin an internal regulator provides a ground?referenced voltage to an external capacitor (c drv1 ), to allow fast recharge of the external bootstrap capacitor (c bst1 ) used to supply power to the power switch gate driver. if the voltage at the drv1 pin goes below the drv uvlo threshold v drvstp , switching is inhibited and the soft?start circuit is reset, until the drv1 pin voltage goes back up above v drvstt . in order for the bootstrap capacitor to stay charged, the switch node needs to be pulled down to ground regularly. in very light load condition, when switcher 1 skips switching cycles to keep the output voltage in regulation, the bootstrap voltage could collapse and the regulator stop switching. to prevent this, an internal minimum load is connected on vout to operate correctly in all cases (it is disconnected in low iq mode, when the stbyb pin is low). a fast?charge circuit ensures the bootstrap capacitor is always charged prior to starting the switcher after it has been enabled. minimum load for a 3.3 v output, an external minimum load is not required. the internal minimum load ensures stability under low?battery conditions. for a 5.0 v output, an external minimum load is required when not using a pre?boost that maintains a minimum 6.8 v on the input. the following chart describes the ways in which the rmin pin is recommended to be used: vout1 pre? boost? vbat condition rmin resistor configuration 5.0 v no vbat < 6.8 v populated resistor connected from vout1 to rmin pin 5.0 v yes vbat set to 6.8 v from pre? boost not populated rmin not connected 3.3 v no vbat < 6.8 v not populated rmin not connected 3.3 v yes vbat set to 6.8 v from pre? boost not populated rmin not connected the rmin resistance (from vout1 to rmin) should be between 27 and 35 . when using an external minimum load, 3 x 100 , ? w resistors are recommended to be placed in parallel from vout1 to the rmin pin of the ic. vin sense NCV97310 rmin vout1 vbat figure 33. internal control for minimum load circuit r min 120
NCV97310 www. onsemi.com 22 current limiting due to the ripple on the inductor current, the average output current of a buck converter is lower than the peak current setpoint of the regulator. figure 34 shows ? for a 4.7 h inductor ? how the variation of inductor peak current with input voltage affects the maximum dc current switcher 1 can deliver to a load. figure 35 shows the same for 2.2 h inductor. figure 34. switcher 1 load current capability with a 4.7 h inductor 0 5 10 15 20 25 30 input voltage, (v) sw1 maximum output current ? worst case (a) 4.5 35 vout1 = 3.3 v vout1 = 5 v 4 3.5 3 2.5 2 1.5 1 0.5 0 figure 35. switcher 1 load current capability with a 2.2 h inductor 0 5 10 15 20 25 30 input voltage, (v) sw1 maximum output current ? worst case (a) 4.5 35 4 3.5 3 2.5 2 1.5 1 0.5 0 vout1 = 3.3 v vout1 = 5 v
NCV97310 www. onsemi.com 23 switchers 2 & 3 enable when a dc logic high (cmos/ttl compatible) voltage is applied to the en2 or en3 pin and the stbyb pin is high switcher 2 or switcher 3, respectively, are allowed to operate. switcher 1 soft start needs to complete before switcher 2 or switcher 3 is allowed to turn on. a dc logic low on en2 or en3 shuts off the respective regulators. soft?start upon being enabled or released from a fault condition, voltage is first established on the vdrv2 pin (for the first of switcher 2 or 3 to be enabled). then a soft?start circuit ramps the switching regulator error amplifier reference voltage to the final value, for a duration t ss independent of the switching frequency (1.4 ms typically). the low?side switch is always turned on first to ensure a proper charge of the bootstrap capacitor. error amplifier the error amplifier is a voltage type amplifier with fixed internal compensation, optimized for the range of input and output voltage combinations. the output voltage of the error amplifier controls the peak inductor current at which the power shuts off (current?mode operation). because the compensation is internally fixed, the value of the upper feedback resistor (in series between the output and the feedback pin) must be 10 k to ensure stability, including in the case of a 1.2 v output, when no lower feedback resistor is used. in addition, it is recommended to use 1 or 2 10 f capacitors on the output, depending on your ripple requirement; and an inductor value between 1 h and 4.7 h (see slope compensation section). slope compensation a fixed slope compensation signal is generated internally and added to the sensed current to avoid increased output voltage ripple due to bifurcation of inductor ripple current at duty cycles above 50% (sub?harmonic oscillations). the fixed amplitude of the slope compensation signal requires the inductor to be greater than a minimum value, dependent on the output voltage, in order to avoid sub?harmonic oscillations. ? for a 5 v output, the recommended inductor value is 4.7 h. ? for 3.3 v or 2.5 v output, the recommended inductor value is 2.2 h. ? for 1.2 v or 1.5 v output, the recommended inductor value is 1.0 h. short circuit frequency foldback during severe output overloads or short circuits, switchers 2 and 3 (independently) automatically enter an auto?recovery burst mode in order to self?protect. when a short?circuit is detected, the switcher disables its output and remains off for the hiccup time and then goes through the power - on reset procedure. if the short has been removed then the output re?enables and operates normally; if, however, the short is still present the cycle begins again. the hiccup mode is continuous until the short is removed. current limiting due to the ripple on the inductor current, the average output current of a buck converter is lower than the peak current setpoint of the regulator. figure 36 shows how the variation of inductor peak current with input voltage affects the maximum dc current switcher 2 or 3 can deliver to a load. figure 36. switcher 2 or 3 load current capability vs. input voltage 3 3.5 4 4.5 6.5 7 7.5 input voltage, (v) sw2 & sw3 maximum output current ? worst case (a) 2.5 8 2 1.5 1 0.5 0 6 5 5.5 v out = 1.2 v (l = 1.0 h) v out = 3.3 v (l = 2.2 h) v out = 1.8 v (l = 1.0 h) output voltage selection the voltage outputs for switcher 2 and switcher 3 are adjustable and can be set with a resistor divider. the fb reference for both switchers is 1.2 v. vout2 (vout3) fbx = 1.2 v r upper r lower figure 37. output voltage selection with feedback divider the upper resistor is set to 10 k and is part of the feedback loop. to maintain stability over all conditions, it is recommended to change the only the lower feedback resistor to set the output voltage. use the following equation: r lower r upper v fb v out v fb
NCV97310 www. onsemi.com 24 some common setups are listed below: desired output (v) vref (v) r upper (k , 1%) r lower (k , 1%) 1.2 1.2 10.0 np 1.5 1.2 10.0 40.0 1.8 1.2 10.0 20.0 2.5 1.2 10.0 9.31 3.3 1.2 10.0 5.76 noise performance for heavy load for heavy load conditions (> 1 a) on the downstream switching outputs, a snubber circuit is recommended for improved noise performance. the following circuit can be used for all output voltage combinations: 100 pf 10 sw2 (sw3) figure 38. rc snubber circuit for noise performance at heavy loads ordering information device package shipping ? NCV97310mw50r2g (5.0 v) qfn32 (pb?free) 5000 / tape & reel NCV97310mw33r2g (3.3 v) qfn32 (pb?free) ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NCV97310 www. onsemi.com 25 package dimensions qfn32 5x5, 0.5p case 488am issue a seating note 4 k 0.15 c (a3) a a1 d2 b 1 9 17 32 e2 32x 8 l 32x bottom view top view side view d a b e 0.15 c pin one location 0.10 c 0.08 c c 25 e notes: 1. dimensions and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from the terminal tip. 4. coplanarity applies to the exposed pad as well as the terminals. plane *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 3.35 0.30 3.35 32x 0.63 32x 5.30 5.30 l1 detail a l alternate terminal constructions l ??? 0.80 a1 ??? a3 0.20 ref b 0.18 d 5.00 bsc d2 2.95 e 5.00 bsc 2.95 e2 e 0.50 bsc 0.30 l k 0.20 1.00 0.05 0.30 3.25 3.25 0.50 ??? max ??? l1 0.15 e/2 note 3 pitch dimension: millimeters recommended a m 0.10 b c m 0.05 c on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer s hall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 NCV97310/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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